Roles and Responsibilities:

• Development of AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS).
• Manage and Review specifications, developing verification plan.
• Manage BOM, netlist generations.
• Interacting with cross functional teams (analog design, digital design) to manage and track updates from and analog and RTL.
• Plan work distribution in the team and ownup few of the critical tasks for hands on execution
• Run and debug SPICE based and digital simulations for AMS SOC/IPs and subsystems
• Understand analog and digital design intent, review simulation setups and ensure correct test conditions. 
• Analyse results using waveform/debug tools and identify root cause for functional mismatch
• Use simulation and waveform tools to speed up debug and improve verification turnaround time
• Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS, and optimize testbenches in tools like Xcelium, Cadence, or Synopsys flows.
• Contribute to improving simulation workslows (run scripts, log parsing, automation, regression)
• Document verification findings, debug notes and simulation methodlogy updates
• Contribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, supervise, train and maintaining effective communication within the team.

Skills we are looking for:

• Expert Knowledge of AMS verification methodologies of 4+ years including mixed signal simulation, assertion and checkers-based verification and analog behavioural modelling
• Advanced proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms
• Excellent skills in Systemverilog, UVM and analog behivioral modelling languages (SV-RNM/Verilog-AMS/Verilog-A)
• Strong fundamentals of Analog and Digital concepts.
• Hands on experience with SPICE and digital simulation tools and debug environments
• Comfortable working in a collaborative team setup with clear communication
• Employ scripting languages (PERL, TCL, Python) for automation and efficiency in verification processes.