This role is for one of the Weekday's clients Salary range: Rs 500000 - Rs 2500000 (ie INR 5-25 LPA) Experience: 2+ yrs Location: Bengaluru Job Type: Full-Time We are looking for a talented Design Verification Engineer with expertise in DDR Verification and UVM-based verification methodologies to join our growing semiconductor engineering team.
In this role, you will be responsible for verifying complex IP and SoC designs, developing robust verification environments, and ensuring first-pass silicon success through comprehensive functional verification.
You will collaborate closely with RTL designers, architects, and validation teams to deliver high-quality, reliable semiconductor solutions across advanced technology nodes.
This position offers an opportunity to work on cutting-edge digital designs, industry-standard protocols, and modern verification methodologies while contributing to the complete verification lifecycle—from planning and environment development to regression, coverage closure, and debugging.
Key Responsibilities Develop and maintain scalable verification environments using SystemVerilog and the Universal Verification Methodology (UVM) .
Verify complex digital IPs and SoCs with a strong focus on DDR memory controller and interface verification .
Create comprehensive verification plans based on design specifications and functional requirements.
Develop reusable testbenches, sequences, scoreboards, monitors, assertions, and coverage models.
Execute functional, regression, and gate-level simulations to validate design functionality and performance.
Analyze simulation results, debug functional failures, and work closely with RTL designers to resolve issues efficiently.
Perform functional coverage analysis and drive coverage closure to ensure complete design verification.
Integrate and utilize industry-standard Verification IPs (VIPs) where applicable.
Verify industry-standard protocols such as DDR , with additional exposure to PCIe or other high-speed interfaces considered advantageous.
Participate in code reviews, verification reviews, and continuous improvement of verification methodologies and automation.
Support pre-silicon verification activities and collaborate with post-silicon validation teams when required.
Contribute to scripting and regression automation to improve verification efficiency and productivity.
What Makes You a Great Fit Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
2+ years of hands-on experience in Design Verification for IP or SoC development.
Strong expertise in DDR Verification using UVM methodology.
Excellent programming skills in SystemVerilog with hands-on experience developing reusable verification components.
Solid understanding of digital design concepts, RTL functionality, and verification methodologies.
Experience creating verification plans, constrained-random testbenches, assertions, functional coverage models, and regression environments.
Familiarity with verification of industry-standard protocols such as DDR , with exposure to PCIe considered an added advantage.
Experience using industry-standard simulation and debugging tools from Synopsys, Cadence, Siemens EDA, or equivalent vendors.
Good understanding of functional coverage, code coverage, assertion-based verification, and coverage-driven verification techniques.
Strong analytical, debugging, and problem-solving skills with attention to detail.
Ability to collaborate effectively with RTL, architecture, validation, and cross-functional engineering teams.
Excellent communication skills and the ability to work in a fast-paced, collaborative semiconductor development environment.
Passion for continuous learning and staying current with evolving verification methodologies, protocols, and semiconductor technologies.
