This role is for one of the Weekday's clients Salary range: Rs 4200000 - Rs 6500000 (ie INR 42-65 LPA) Experience: 7+ yrs Location: Bengaluru Job Type: Full-Time We are looking for an experienced Physical Design Lead to drive the complete RTL-to-GDSII implementation for advanced ASIC and SoC designs.
This role requires a strong technical leader who can manage complex physical design activities, mentor engineering teams, and collaborate with cross-functional stakeholders to deliver high-quality silicon.
The ideal candidate will have deep expertise in physical design methodologies, timing closure, ECO implementation, physical verification, and EDA tools, along with a passion for driving innovation through automation and AI-driven design optimization.
Key Responsibilities Lead the complete RTL-to-GDSII physical design flow, ensuring timely delivery of high-quality designs.
Execute and manage floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical signoff activities.
Drive Engineering Change Order (ECO) implementation and optimize designs to meet evolving project requirements.
Perform and resolve physical verification issues, including DRC and LVS, to ensure design manufacturability and quality.
Optimize power, performance, and area (PPA) while achieving timing and signal integrity goals.
Utilize industry-standard EDA tools such as ICC2, Fusion Compiler, Innovus, PrimeTime, and Tempus for physical design implementation and analysis.
Apply AI/ML techniques to improve floorplanning, placement, routing, congestion reduction, timing closure, and ECO automation.
Develop scripting and automation solutions to improve design productivity and streamline physical design workflows.
Collaborate closely with RTL, STA, DFT, Verification, and other cross-functional teams throughout the design lifecycle.
Mentor and guide engineering teams while managing project schedules, deliverables, and technical execution.
Monitor project progress, communicate status effectively, and proactively resolve technical challenges.
What Makes You a Great Fit Strong hands-on experience leading the complete RTL-to-GDSII physical design flow for ASIC/SoC projects.
Expertise in timing closure, ECO implementation, and physical verification (DRC/LVS).
Proficiency with industry-leading EDA tools including ICC2, Fusion Compiler, Innovus, PrimeTime, and Tempus .
Strong understanding of floorplanning, placement, CTS, routing, power optimization, and physical signoff methodologies.
Experience applying AI/ML techniques to enhance physical design efficiency and optimize PPA.
Familiarity with Design for Test (DFT) concepts and post-silicon validation considerations.
Strong scripting and automation skills using languages such as TCL, Python, or Shell to improve design productivity.
Excellent analytical and problem-solving skills with the ability to resolve complex timing and physical design challenges.
Proven experience leading engineering teams, mentoring designers, and managing multiple project deliverables.
Strong communication and stakeholder management skills with the ability to collaborate effectively across cross-functional teams.
