General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

About the Role

We are looking for a motivated and detail-oriented AMS Design Verification Engineer to join our RFIC verification team. In this role, you will contribute to the functional verification of analog and mixed-signal blocks used in WAN, 6G, 5G , SDR, IoT and GPS radio subsystems, working across Real Number Models, RTL, Gate-Level , Gate-PA Netlists on complex mixed-signal SoCs.

Responsibilities

Verification Planning & Modeling

• Develop a thorough understanding of analog & mixed signal block functionality and translate it into structured verification plans
• Build high-level behavioral models using SystemVerilog Real Number Modeling (RNM) and Verilog-AMS

Testbench Development & Execution

• Design and implement UVM/SystemVerilog-based testbenches with self-checking architectures, scoreboards, and functional coverage
• Set up, run, and debug simulation test cases across RTL, Gate-Level, and Gate-PA Netlists
• Configure and execute AMS co-simulation environments integrating SPICE/Spectre with digital simulators

Debug & Analysis

• Perform in-depth debug of analog and mixed-signal circuits using tools such as Cadence xcelium, Verisium debug, Simvision, and Virtuoso etc
• Analyze simulation results, identify root causes of failures, and collaborate with design engineers to drive closure
• Support regression management, bug tracking, and coverage analysis to achieve signoff metrics

Automation & Scripting

• Develop and maintain Python, Shell, and TCL scripts to automate verification workflows, regression pipelines, and reporting tasks

Collaboration & Post-Silicon

• Work closely with Analog, Digital Design, DV, Software and DFT engineers in a fast-paced, tape-out-driven environment
• Provide support during post-silicon bring-up and correlation activities

Minimum Qualifications

• Bachelor’s degree in electrical engineering, Electronics Engineering, Computer Engineering, or a related field (Master’s degree preferred)
• 1–3 years of hands-on experience in mixed-signal or analog-digital verification, or equivalent relevant work

Preferred Skills

• Working knowledge of Electrical circuit analysis
• Basic knowledge of Analog & Digital design fundamentals
• Basic knowledge of AMS verification fundamentals.
• Working knowledge of Verilog, SystemVerilog, UVM — testbench architecture and methodology
• Working knowledge of SV Real Number Modeling (RNM) and/or Verilog-AMS behavioral modeling
• Basic knowledge of core RF/analog and mixed-signal building blocks, including Synthesizers, Amplifiers, PLLs, LNAs, ADCs, DACs, LDOs, Filters, Clock gen, Mixers etc
• Basic knowledge of any programming interfaces or communication protocols.
• Proficiency in Python, TCL, and Shell scripting for verification automation is a plus
• Experience with Cadence EDA tools (Xcelium, SimVision, Verisum debug, Virtuoso) is a plus
• Exposure to SPICE/Spectre for analog circuit analysis is a plus

Keywords

AMS Verification, Mixed-Signal Verification, Functional Verification, RF, Analog , Verilog/SystemVerilog, RNM Behavioral Modeling, UVM, Verilog-AMS, Cadence Tool, 5G, 6G, RFIC, SoC Verification

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