This role is for one of the Weekday's clients Salary range: Rs 1300000 - Rs 2600000 (ie INR 13-26 LPA) Experience: 5+ yrs Location: Pune, Maharashtra, India Job Type: Full-Time We are seeking an experienced DFT (Design for Test) Engineer to support end-to-end test implementation and validation for complex semiconductor designs.
The ideal candidate will have strong expertise in scan insertion, ATPG, pattern retargeting, DFT verification, and post-silicon debug across block and SoC levels.
In this role, you will collaborate with Design, Verification, Physical Design, and ATE teams to implement robust DFT methodologies, improve test coverage, and ensure high-quality silicon.
You will also contribute to DFT architecture, pattern generation, and silicon bring-up while driving continuous improvements in test quality and efficiency.
Key Responsibilities Perform scan insertion and ATPG for block-level designs and manage pattern retargeting at the top level.
Implement and verify DFT logic using industry-standard tools such as Tessent, TestMAX, or Modus.
Execute gate-level DFT verification with and without timing using simulators such as VCS or NCSim.
Generate, validate, and deliver production-ready test patterns for ATE implementation.
Improve fault coverage by identifying coverage gaps and implementing innovative DFT strategies.
Integrate and verify JTAG, MBIST, and LBIST architectures for enhanced testability.
Debug simulation failures, scan issues, DRC violations, and pattern-related problems throughout the design cycle.
Support post-silicon bring-up activities by analyzing failing patterns and resolving test-related issues.
Collaborate closely with Design, Verification, Physical Design, and Manufacturing teams to ensure successful DFT implementation and silicon validation.
Mentor junior engineers and contribute to process improvements, documentation, and best practices in DFT methodology.
What Makes You a Great Fit Strong experience in Scan Insertion , ATPG , and Pattern Retargeting for block-level and top-level designs.
Hands-on expertise with DFT implementation and verification tools such as Tessent , TestMAX , or Modus .
Good understanding of DFT verification, fault coverage analysis, and gate-level simulation.
Experience with JTAG , MBIST , and LBIST insertion, verification, and pattern generation.
Familiarity with simulation tools such as VCS or NCSim for DFT validation.
Strong debugging skills for scan chain issues, DRC violations, and post-silicon test failures.
Knowledge of semiconductor test methodologies, ATE pattern delivery, and silicon bring-up.
Ability to collaborate effectively with cross-functional engineering teams and drive technical solutions.
Strong analytical, problem-solving, and communication skills.
Passion for delivering high-quality, testable semiconductor designs while continuously improving DFT processes and coverage.
