This role is for one of the Weekday's clients Salary range: Rs 4000000 - Rs 25000000 (ie INR 40-250 LPA) Experience: 10+ yrs Location: Bangalore, Bengaluru Job Type: Full-Time We are seeking an experienced Standard Cell Circuit Design Engineer with deep expertise in designing high-performance, low-power standard cell libraries for advanced semiconductor technology nodes.
This role is ideal for professionals who have a strong background in transistor-level circuit design, library characterization, validation, and optimization, along with the ability to collaborate across layout, CAD, PDK, and physical design teams.
The successful candidate will play a key role in developing robust standard cell libraries that meet stringent power, performance, and area (PPA) requirements for next-generation semiconductor products.
This position offers the opportunity to work on cutting-edge FinFET technologies while contributing to high-quality silicon development through innovative circuit design and technical leadership.
Key Responsibilities Design and develop high-performance, low-power, and area-efficient standard cell libraries for advanced technology nodes.
Create and optimize a wide range of standard cells, including combinational and sequential logic, flip-flops, latches, clock gating cells, level shifters, isolation cells, retention cells, multi-bit flip-flops, and clock buffers.
Perform transistor-level circuit design, simulation, optimization, and verification using industry-standard EDA tools.
Optimize circuits for timing, leakage power, dynamic power consumption, signal integrity, noise immunity, and overall reliability.
Collaborate closely with layout engineers to achieve optimal layouts while ensuring compliance with DRC, LVS, and ERC requirements.
Drive library characterization, validation, and quality assurance across multiple process, voltage, and temperature (PVT) corners.
Analyze and resolve issues related to process variation, EM/IR, aging effects, ESD, latch-up, and reliability.
Support the generation, validation, and maintenance of Liberty (.
lib), LEF, GDSII, CDL, SPICE, and Verilog library deliverables.
Work with CAD, characterization, PDK, and physical design teams to integrate and release production-ready standard cell libraries.
Participate in silicon bring-up, debugging, validation, and correlation of silicon results with simulation data.
Provide technical guidance and mentor junior engineers while contributing to continuous improvements in library development methodologies.
What Makes You a Great Fit Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
10+ years of hands-on experience in Standard Cell Circuit Design and library development.
Strong expertise in CMOS transistor-level circuit design and optimization techniques.
Experience designing a wide range of standard cells, including logic gates, flip-flops, latches, clock gating cells, level shifters, isolation cells, retention cells, and clock distribution components.
Solid understanding of setup/hold timing, power optimization, noise analysis, signal integrity, and reliability considerations.
Hands-on experience with advanced FinFET technologies such as 3nm, 5nm, 7nm, or similar process nodes.
Proficiency with industry-standard EDA tools including Cadence Virtuoso, Spectre, HSPICE, Liberate, PrimeLib, Calibre, StarRC, and related circuit design and verification tools.
Strong knowledge of library characterization, circuit verification, silicon validation, and variation-aware design methodologies.
Excellent analytical, debugging, and problem-solving skills with a focus on delivering high-quality standard cell libraries.
Strong communication, collaboration, and leadership abilities with experience working effectively in cross-functional engineering teams.
