Join our new ASIC top level verification team.

We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.

As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.

You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.

We are looking for people with focus in various areas in ASIC TLV. Exactly what you will do depends on your experience and the needs in the different projects, but typically includes

• SoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more.
• Preparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms.
• Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier.
  As input you have documents and information from interaction with various type of stakeholders.
• Participate in specification and development of software driven tests written in C.
• Debug RTL designs with help of EDA simulation tools and SW debuggers.
• But also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation
• Beside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab.
• In case you lack experience of some platform you are expected to develop skills for such tasks.
• Contribute to keeping tests clean in the CI regression running on our four platforms.
• who occasionally can develop of tests involving UVM VIPs (used in some of our tests)
• who from time to time will work with gate level simulation (GLS)
• to work with formal connectivity verification
• to compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium
• interested in scripting and in developing and maintaining the TLV CI flow in projects, including visualization of results.

SW/C testcase developers, some with SystemVerilog / UVM experience.

Preferably experience in one or several areas:

• AMBA protocols
• ARM cores/MCUs or processors
• JTAG and Coresight
• External interfaces: PCIe, XGMII/Ethernet, xSPI, I3C, UART, GPIO
• Memory interfaces: DDR, HBM
• Clock and reset verification

Soft Skills

• Open, inclusive mindset, embracing diversity in culture, nationality, gender, etc.
• Collaborative approach, with a focus on team productivity and mutual growth.
• Strong drive for innovation, with a proactive interest in refining verification methodologies.
• Clear communication skills for effective teamwork and coordination across diverse teams.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”