Job description
This role is for one of the Weekday's clients Min Experience: 4+ years Location: Bengaluru JobType: full-time We are looking for a highly motivated Senior Physical Design Engineer with 4–8 years of experience in ASIC Physical Design, Place & Route (PnR), and Timing Closure.
The ideal candidate will take ownership of block-level physical design activities from floorplanning to signoff while ensuring high-quality, timely project delivery.
This role requires strong technical expertise in physical implementation tools, timing analysis, and physical verification, along with the ability to mentor team members and drive project execution.
Key Responsibilities Lead and manage the complete physical design implementation of multiple block-level designs from floorplanning through signoff.
Own block-level Place & Route (PnR), timing closure, and physical verification activities while ensuring adherence to quality, power, performance, and area (PPA) goals.
Guide and mentor team members in resolving complex PnR, congestion, routing, timing, and implementation challenges.
Perform floorplanning, placement optimization, clock tree synthesis (CTS), routing, and physical optimization using industry-standard EDA tools.
Drive timing convergence across multiple process corners and operating modes using static timing analysis methodologies.
Collaborate with RTL, synthesis, DFT, verification, and design teams to resolve implementation issues and improve overall design quality.
Analyze and close setup/hold timing violations, signal integrity issues, and optimization bottlenecks.
Execute physical verification including DRC, LVS, ERC, IR Drop, and Electromigration (EM) analysis, ensuring successful signoff.
Develop and maintain implementation flows, automation scripts, and productivity tools to improve design efficiency.
Manage project schedules, track milestones, communicate progress, and proactively identify project risks.
Review timing constraints, validate implementation assumptions, and ensure consistency throughout the design cycle.
Prepare technical documentation and provide regular status updates to stakeholders.
RequirementsQualifications Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI, or a related discipline.
4–8 years of hands-on experience in ASIC Physical Design for advanced technology nodes.
Required Skills Strong experience managing multiple block-level physical design implementations.
Expertise in floorplanning, placement, clock tree synthesis, routing, optimization, and physical signoff.
Hands-on experience with ICC2 and/or Innovus for complete Place & Route implementation.
Strong timing closure expertise using PrimeTime and/or Tempus .
Experience performing physical verification using Calibre , ICV , or PVS .
Experience analyzing and resolving IR Drop and Electromigration issues using RedHawk and/or Voltus .
Solid understanding of timing constraints, SDC creation, validation, and optimization.
Ability to manage multiple design blocks simultaneously while meeting aggressive project schedules.
Strong debugging, analytical, and problem-solving capabilities.
Experience with scripting and automation using Tcl, Shell, Python, Perl, or similar languages.
Excellent communication skills with the ability to coordinate across cross-functional engineering teams.
Proven experience in project planning, schedule tracking, and delivery reporting.
Good-to-Have Skills Advanced Physical Design (PnR) methodologies.
Timing Closure using PrimeTime and Tempus.
Floorplanning optimization techniques.
Expertise with ICC2 and Innovus implementation flows.
Experience working on low-power and high-performance SoC designs.
Knowledge of advanced process nodes and signoff methodologies.
This job post has been translated by AI and may contain minor differences or errors.
