Synthesis- Staff Engineer

Company:Qualcomm India Private Limited
Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm Chennai is seeking a highly motivatedSynthesis (Design Implementation) Engineerto drive synthesis and low-power implementation for complex SoC and subsystem designs. The candidate will work closely with Design, Physical Design, DFT, and Timing teams to achieve competitive Power, Performance, and Area (PPA) targets on advanced technology nodes.

Key Responsibilities

• Lead and manage synthesis deliverables across multiple blocks/subsystems, ensuring schedule, quality, and tape out commitments are met.
• Mentor and technically guide team members on timing closure, UPF methodologies, advanced-node implementation challenges, and debug strategies
• Drive execution reviews, risk assessment, and closure plans for project milestones.
• Coordinate across RTL, DFT, Physical Design, STA, and Verification teams to resolve cross-functional issues and improve design convergence.
• Define and drive synthesis methodologies, best practices, and flow improvements across the team.
• Contribute to resource planning, execution tracking, and prioritization of team deliverables.

• Run quality checks includingcheck_design, check_timing, Lint, CDC, ERC, and support MTBF-related fixes.

Required Skills

• Strong experience with Physical and low power aware synthesis usingSynopsys Fusion Compiler/Design CompilerorCadence Genus.
• Implement and validateUPF-based low-power architectures, including isolation cells, level shifters, retention cells, and power switches
• Develop and maintainSDC constraints, perform Pre-STA analysis, and drive pre-layout timing convergence.
• Expertise inPrimeTime/Tempus,UPF,CLP, andFormality/Conformal/Conformal ECO.
• Good understanding ofmulti-voltage designs, low-power methodologies, and timing closure
• Develop automation and flow improvements usingAI agents,TCL, Perl, Python, and Shell scripting

Preferred Qualifications

• Experience on advanced nodes (6nm/5nm/4nm/3nm or equivalent).
• Ownership of synthesis for blocks/subsystems with2M+ cells.
• Expertise inUPF, Multi voltage Designs, POCV/AOCVandvariation-aware high speedtiming analysis.
• Experience with flat-level signoff flows, LEC, CLP and physical synthesis methodologies.
• Ability to independently drive synthesis and low-power closure through tape out
• IO timing closure

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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